The present invention relates to memory integrated circuits, and more particularly to memory circuits that ignore storage errors in random access memory.
Semiconductor memory devices have been widely used in electronic systems to store data. There are generally two types of semiconductor memories, including non-volatile and volatile memories. A volatile memory device, such as a Static Random Access Memory (SRAM) or a Dynamic Random Access Memory (DRAM) device, loses its data when the power applied to it is turned off. In contrast, a non-volatile semiconductor memory device, such as a Flash, Erasable Programmable Read Only Memory (EPROM) or a magnetic random access memory (MRAM), retains its charge even after the power applied thereto is turned off. Therefore, where loss of data due to power failure or termination is unacceptable, a non-volatile memory is used to store the data.
FIG. 1A is a simplified cross-sectional view of a magnetic tunnel junction (MTJ) structure 10 used in forming a spin transfer torque (STT) MRAM cell. MTJ 10 is shown as including, in part, a reference layer 12, a tunneling layer 14, and a free layer 16. Reference layer 12 and free layer 16 are ferromagnetic layers. Tunneling layer 14 is a nonmagnetic layer. The direction of magnetization of reference layer 12 is fixed and does not change. The direction of magnetization of free layer 16, however, may be varied by passing a sufficiently large current through the MTJ structure. In FIG. 1A, reference layer 12 and free layer 16 are assumed to have the same magnetization direction, i.e., they are in a parallel state. In FIG. 1B, reference layer 12 and free layer 16 are assumed to have opposite magnetization directions, i.e., they are in an anti-parallel state. In FIG. 1C, reference layer 12 and free layer 16 are assumed to have the same magnetization direction perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14. In FIG. 1D, reference layer 12 and free layer 14 are assumed to have opposite magnetization directions perpendicular to a plane defined by the interface of free layer 16 and tunneling layer 14.
To switch from the parallel state, as shown in FIG. 1A, to the anti-parallel state, as shown in FIG. 1B, the voltage potential of reference layer 12 is increased relative to that of free layer 16. This voltage difference causes spin polarized electrons flowing from free layer 16 to reference layer 12 to transfer their angular momentum and change the magnetization direction of free layer 16 to the anti-parallel state, as shown in FIG. 1B. To switch from the anti-parallel state to the parallel state, the voltage potential of free layer 16 is increased relative to that of reference layer 12. This voltage difference causes spin polarized electrons flowing from reference layer 12 to free layer 16 to transfer their angular momentum and change the magnetization direction of free layer 16 to the parallel state, as shown in FIG. 1A.
To switch from the parallel state to the non-parallel state or vice versa, the voltage applied to MTJ 10 and the corresponding current flowing through MTJ must be greater than a respective pair of threshold values. The voltage that must exceed a threshold voltage in order for the switching to occur is also referred to as the switching voltage Vc. Likewise, the current that must exceed a threshold current in order for the switching to occur is referred to as the switching current Ic. As is well known, when free layer 16 and reference layer 12 have the same magnetization direction (parallel state), MTJ 10 has a relatively low resistance. Conversely, when free layer 16 and reference layer 12 have the opposite magnetization direction (anti-parallel state), MTJ 10 has a relatively high resistance. Due to the physical properties of an MTJ, the critical current required to change the state of an MTJ from a parallel to an anti-parallel is often greater than the critical current required to change the state of the MTJ from an anti-parallel to a parallel state.
FIG. 2A shows an MTJ 10 and an associated select transistor 20 together forming an STT-MRAM cell 30. Transistor 20 is often an NMOS transistor due to its inherently higher current drive, lower threshold voltage, and smaller area relative to a PMOS transistor. As is described further below, the current used to write a “1” in MRAM 30 is different than the current used to write a “0”. The asymmetry in the direction of current flow during these two write conditions is caused by the asymmetry in the gate-to-source voltage of transistor 20. Accordingly, a write driver adapted to deliver sufficient current to write a “0”, may not be able to provide enough current to write a “1”. Similarly, a write driver adapted to deliver sufficient current to write a “1” may deliver a current that is greater than what would otherwise be an acceptable current level to write a “0”.
In the following description, an MRAM cell is defined as being in a logic “0” state when the free and reference layers of its associated MTJ are in a parallel (P) state, i.e., the MTJ exhibits a low resistance. This low resistance state is also alternatively shown as Rlow or RP state. Conversely, an MRAM cell is defined as being in a logic “1” state when the free and reference layers of its associated MTJ are in an anti-parallel (AP) state, i.e., the MTJ exhibits a high resistance. This high resistance state is also alternatively shown as Rhigh or RAP state. Furthermore, in the following, it is assumed that the reference layer of the MTJ faces its associated select transistor, as shown in FIG. 2A. Therefore, in accordance with the discussion above, a current flowing along the direction of arrow 35 (the up direction) (i) either causes a switch from the P state to the AP state thus to write a “1”, (ii) or stabilizes the previously established AP state of the associated MTJ. Likewise, a current flowing along the direction of arrow 40 (the down direction) (i) either causes a switch from the AP state to the P state thus to write a “0”, (ii) or stabilizes the previously established P state of the associated MTJ. It is understood, however, that in other embodiments this orientation may be reversed so that the free layer of the MTJ faces its associated select transistor. In such embodiments (not shown), a current flowing along the direction of arrow 35 (i) either causes a switch from the AP state to the P, (ii) or stabilizes the previously established P state of the associated MTJ. Likewise, in such embodiments, a current flowing along the direction of arrow 40 (i) either causes a switch from the P state to the AP state, (ii) or stabilizes the previously established AP state. FIG. 2B is a schematic representation of MRAM 30 of FIG. 2A in which MTJ 10 is shown as a storage element whose resistance varies depending on the data stored therein. The MTJ changes its state (i) from P to AP when the current flows along arrow 35, and (ii) from AP to P when the current flows along arrow 40.
As described above, the voltage required to switch an MTJ from an AP state to a P state, or vice versa, must exceed a critical value Vc. The current corresponding to this voltage is referred to as the critical current Ic. FIG. 3 represents the variation in the MTJ state (or its resistance) during various write cycles. To transition from the P state (low resistance state) to AP state (high resistance state), a positive voltage of Vc is applied. Once in the AP state, removing the applied voltage does not affect the state of the MTJ. Likewise, to transition from the AP state to the P state, a negative voltage of Vc is applied. Once in the P state, removing the applied voltage does not affect the state of the MTJ. The resistance of the MTJ is Rhigh when it is in AP state and receives no or very small voltage. Likewise, the resistance of the MTJ is Rlow when it is in P state and receives no or very small voltage.
FIG. 4A shows an MTJ 10 being programmed to switch from an anti-parallel state (i.e., high resistance state, or logic “1” state) to a parallel state so as to store a “0” (i.e., low resistance state, or logic “0” state). It is assumed that MTJ 10 is initially in a logic “1” or AP state. As described above, to store a “0”, a current Ic greater than the critical current is caused to flow through transistor 20 in the direction of arrow 40. To achieve this, the source node (SL) of transistor 20 is coupled to the ground potential via a resistive path (not shown), a positive voltage Vpp is applied to the gate node (WL or wordline) of transistor 20, and a positive voltage Vcc is applied to the drain node (BL or bitline) of transistor 20.
FIG. 5 is an exemplary timing diagram of the voltage levels at nodes WL, SL, SN and BL during write “0” operation, occurring approximately between times 25 ns and 35 ns, and write “1” operation, occurring approximately between times 45 ns and 55 ns, for a conventional MTJ such as MTJ 10 shown in FIGS. 4A and 4B. Supply voltage VCC is assumed to be 1.8 volts. Signal WL, as well as signal CS which is a column select signal, are shown as having been boosted to a higher Vpp programming voltage of 3.0 volts. During the write “0” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 1.43 V, 0.34 V, and 0.88 V respectively. During the write “1” operation, the voltages at nodes BL, SL and SN are shown as being approximately equal to 0.23 V, 1.43 V, and 0.84 V respectively. Although not shown, for this exemplary computer simulation, the currents flowing through the MTJ during write “0” and “1” operations are respectively 121 μA and 99.2 μA.
FIG. 4B shows an MTJ being programmed to switch from a parallel state to an anti-parallel state so as to store a “1”. It is assumed that MTJ 10 is initially in a logic “0” or P state. To store a “1”, a current L greater than the critical current is caused to flow through transistor 20 in the direction of arrow 35. To achieve this, node SL is supplied with the voltage Vcc via a resistive path (not shown), node WL is supplied with the voltage Vpp, and node BL is coupled to the ground potential via a resistive path (not shown). Accordingly, during a write “1” operation, the gate-to-source voltage of transistor 20 is set to (VWL-VSN), and the drain-to-source voltage of transistor 20 is set to (VSL-VSN).
Because the gate-to-source and drain-to-source voltages of transistor 20 are higher under the conditions described with reference to FIGS. 4A and 5 than they are under the conditions described with reference to FIGS. 4B and 5, the corresponding current flow through the MTJ is higher when attempting to write a logic “0” than a logic “1”. Accordingly, the voltages designed to generate the critical current needed to carry out a write “0” operation may not be sufficient to carry out a write “1” operation. An undesirable asymmetry thus exists in the current levels during write “1” and write “0” operations. Consequently, a transistor size selected to provide sufficient current to write a “0” may not provide enough current to write a “1”. Alternatively, a larger transistor size selected to provide the required current to write a “1”, may result in generation of excessive current when writing a “0”. Such an excess current may damage the tunneling layer of the MTJ shown in FIG. 1.
During redundancy operation, a memory chip may be tested and repaired at the factory (or by the seller) by determining the address locations of defective cells. The defective address locations are then mapped out of the final usable address space by replacing entire rows and/or columns in the regular memory array with redundant rows and/or columns provided on the same chip. The redundancy mapping is accomplished by setting content addressable memory (CAM) bits granular only at the row and/or column level within the addressing/decoding circuitry. The redundancy operation is normally done by special test operation modes that are not made available to the memory's end-user so the memory producer may maintain control of the product quality. Once in the field, memory address locations mapped out by redundancy stay mapped out for the life of the part. In contrast, during normal write operation by an end-use, memory address locations are granular by individual cell and reusable (except for the case of permanently altered memory such as ROM or PROM). Thus, redundancy operations are different than normal write operations done by the end-user.
Error correction codes (ECC) are used to logically process the values of multiple logical bits that are grouped in fixed sized blocks, such as a byte, to be written in a memory. The ECC logic generates additional encoded logical bit values called a checksum or ECC to be stored additionally with the original byte. Each value in the checksum or ECC may be different depending on the values in the byte and the encoding algorithm. The ECC encoding takes additional circuitry and slows performance but enables errors in the original byte to be detected and/or corrected depending on the number of bit errors in the byte, type of encoding and number of additional bits used.